Numerical and Experimental Comparison of the Control Techniques Quasi-Sliding, Sliding and PID, in a DC-DC Buck Converter

Nicolás Toro García; Yeison Alberto Garcés Gómez; Fredy Edimer Hoyos Velasco

Eléctrica

Comparación numérica y experimental de técnicas de control quasi-sliding, sliding y PID en un convertidor buck.

Nicolás Toro García ntoroga@unal.edu.co

Universidad Nacional de Colombia Sede Manizales, Colombia

Yeison Alberto Garcés Gómez ygarces@ucm.edu.co

Universidad Nacional de Colombia Sede Manizales, Colombia

Fredy Edimer Hoyos Velasco fehoyosve@unal.edu.co

Universidad Nacional de Colombia Sede Medellín, Colombia

Numerical and Experimental Comparison of the Control Techniques Quasi-Sliding, Sliding and PID, in a DC-DC Buck Converter

Scientia Et Technica, vol. 23, núm. 1, pp. 25-33, 2018

Universidad Tecnológica de Pereira

Recepción: 18 Septiembre 2018

Aprobación: 30 Marzo 2019

Abstract: In this paper the Sliding Mode Control (SMC), PID and ZAD (Zero Average Dynamic) strategies are applied to an electronic DC-DC power converter. Time behavior for each controller is shown for numerical solution and experimental realization. The results in SMC and PID are contrasted with a ZAD-FPIC controller combined with a recently developed strategy named FPIC (Fixed Point Induction Control). Stability in SMC is guaranteed by the Lyapunov theorem. The PID controller is designed in an analytical way using pole placement. The main problem with the physical realization was the sample and hold in the variable acquisition system, in addition to time delay introduced by the computing process. From a practical point of view, the ZAD-FPIC technique has advantages no shown by PID and SMC working with sample and hold, these advantages have been corroborated experimentally. The designs have been tested in an RCP (Rapid Control Prototyping) system based on DSP from the dSPACE platform. Both numerical performance and experimental performance agree.

Keywords: Sliding mode control, ZAD-FPIC, PID controller analytical design, numerical and experimental results, delay time, DPWM, DC-DC buck converter, Lyapunov analysis.

Resumen: En este artículo son aplicadas varias técnicas de control para un convertidor reductor DC-DC estas son: control por modos deslizantes (SMC), PID y promediado de dinámica cero (ZAD). El comportamiento en el tiempo para cada controlador es mostrado tanto numéricamente como experimentalmente. Los resultados de SMC y PID son contrastados con la estrategia de control ZAD-FPIC esta última es combinada con una reciente técnica de control llama FPIC (control por inducción al punto fijo). La estabilidad de SMC es garantizada mediante teorema de Lyapunov. El control PID es diseñado de forma analítica usando desplazamiento de polos. El principal problema en la realización experimental fue la velocidad de muestreo y retención de las variables adquiridas del sistema, adicionalmente el tiempo de retardo presente en los procesos de procesamiento. Desde el punto de vista práctico la técnica de control ZAD-FPIC tiene ventajas en comparación con PID y SMC cuando se trabaja con muestreo y retención, esas ventajas han sido corroboradas experimentalmente. Los experimentos han sido probados en sistema RCP (prototipo rápido de control) específicamente en una DSP de la compañía dSPACE, al final tanto los resultados de la simulación numérica y la experimental son muy similares.

Palabras clave: Control por modos delizantes, ZAD-FPIC, diseño de control analítico PID, resultados numéricos y experimentales, retardo de tiempo, DPWM, convertidor DC-DC reductor, análisis de estabilidad por Lyapunov.

I. INTRODUCTION

Nowadays, digital PWM (DPWM) is increasingly used for control electronic power converters. This is because it has, because of a number of potential advantages, including: programmability, ability to interface with digital systems, a potentially faster design process, lower sensitivity to parameter variations, reduction or elimination of external passive components, calibration or protection algorithms. Likewise the possibility of implementing nonlinear control techniques in order to improve dynamic responses has been highlighted as a potential advantage of digital control [1], [2], [3]. DPWM has enabled practical realizations of high frequency digital controllers for dc-dc converters (e.g., [4], [5]). In [6] a nonlinear control, which is triggered every T period, is presented.

However, the DPWM also has disadvantages. It is affected by two limitations: quantization effects [7], [8], namely the A/D converter, and delays in the control loop [9]. These can cause undesirable limit-cycle oscillations. In [2] the presence of steady-state limit cycles in DPWM converters is discussed, and conditions on the control law and the quantization resolution for their elimination are suggested. In [1] an approach to improve dynamic responses of digitally controlled DC-DC converters using no uniform analog-to-digital (A/D) quantization of the output voltage error is presented.

Due to the high cost of Digital Signal Processor (DSP), applications are limited to high power applications like motor drives and expensive systems. In [3] a diagrammatic method to find out a minimum requirement of digital controller with considerations on both time sampling and quantization resolution dimensions is provided.

Nowadays, the ZAD control technique has been studied in the literature [6, 10, 11, 12]. In particular, in [10]

the transition to chaos was found through analytical and numerical results, as the parameter varied, on the other hand, the development and application of a new control technique FPIC (Fixed Point Induction Control) has been shown in [11, 12, 13, 14, 15, 16]. This technique allows us to stabilize unstable orbits in a simple way. In [16] introduce the load estimator by means of LMS, to make ZAD and FPIC control feasible in load variation conditions.

In this paper the Sliding Mode Control (SMC), PID and ZAD (Zero Average Dynamic) strategies are applied at a DC-DC buck converter. The results in SMC and PID are contrasted with a ZAD controller combined with a recently developed strategy named FPIC. The designs have been tested in a DSP from the dSPACE platform. Both numerical performance and experimental performance agree.

The paper is organized as follows: section 2 describes the proposed model. Section 3 describes mathematical considerations of the system and the SMC, PID and ZAD-FPIC strategies. Section 4 is devoted to the results and finally, section 5 presents the conclusions.

II. PROPOSED MODEL

Figure (1) shows the global system, the software part is fully realized in a DSP (DS1104) using Matlab-Simulink and executed in real time. The hardware was implemented with electronic component and buck power converter with parasitic elements is shown in Figure (2). Output voltage regulation $υ_{c} = V_{o}$ can be done with this configuration, $V_{f d}$ is the diode forward voltage, $r_{s}, r_{M}, r_{M e d}, r_{L}$ , are the internal resistance of the source, the MOSFET, the current sensor and the inductor, respectively

Figure 1.
Block diagram of experiment for SMC, PID and ZAD-FPIC controllers.
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Figure 2.
Buck power converter.
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III. MATHEMATICAL CONSIDERATIONS

In this section, we present the general tools needed to analyze and control the power converter.

A. SYSTEM MODEL.

This system can be expressed in a mathematical way by the following set of differential equations: when the switch is ON, it is described by equation (1); when the switch is OFF, it is described by equation (2).

(1)

(2)

The equations (1) and (2) they can be written in this way with and . The control scheme used in this work corresponds to a Centered Pulse Width Modulation (CPWM) [13, 14, 16, 19]. The system operates as:

(3)

Where $d_{k}$ is the duty cycle, and it is obtained as $d_{k} = \frac{D_{k}}{T}$ , with $T = 200 μ s$ is the sampling time and $D_{k}$ is the duty cycle into range the 0 at 1.

B. SLIDING MODE CONTROL TECHNIQUE

The advantages of this control structure lie in the fast dynamic response and high robustness with respect to disturbances and parameter variations [17].

Let $x_{1 r e f} = υ_{r e f}$ be the reference of output voltage and (4) the voltage tracking error.

(4)

Define state variables $z_{1} = e$ and $z_{2} = \overset{\cdot}{e}$ . The $υ_{c}$ equation of the DC buck converter (1) with respect to the states $z_{1}$ , $z_{2}$ is given by $\overset{\cdot}{z} = z_{2}$

(5)

Where , , are constant values. The linear part of (5) is perturbed by , depending on the desired output voltage $v_{c}$ . Since (5) is a second order system, the switching function is designed as:

(6)

With $c$ being a positive constant. The associated controller is defined as:

(7)

Where $u_{o}$ is the link voltage. According to these equations, the voltage tracking error $z_{1}$ decays exponentially after the sliding mode occurs in the manifold . Where constant $c$ determines the rate of the convergence. The system motion in sliding mode is independent of parameters $a_{1}$ , $a_{2}$ , $b$ and disturbances in $f (t)$ .

When the output trajectory is not on the sliding surface the controller must drive the output trajectory to the sliding mode . The system under this condition is said to be on the reaching phase. For this purpose, the Lyapunov function is selected as:

The

To enforce the sliding mode, control gain $u_{o}$ should be selected so that .

For the control command

Then the link voltaje $u_{o}$ should satisfy the condition

(8)

For sliding mode to exist. Then, after a finite time interval, the system status will reach the sliding manifold . Thereafter, the system response depends only on the design parameter $c$ .

Figure (3) shows the SMC control simulation diagram on Matlab-Simulink, using (6) and (7). In figure lowest part the A/D converter is simulated with Zero-Order Hold, 12 bits Quantizer and Unit Delay. In 9 bits Quantizer block the quantization effect over DPWM generator is considered.

Figure 3.
Sliding Mode Control simulation.
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C. PID CONTROLLER.

For the PID controller design, a pole placement method is used, It starts with a desired behavior, determined by the second order canonical equation, which should match the characteristic equation of the closed loop system with PID to find the constants $K_{p}$ , $K_{d}$ , $K_{i}$ .

For desired response ms,

Second order canonical equation (desired behavior):

With poles on:

In the case where the switch is closed, in buck converter model (1), we can rewrite the state equation as:

(9)

Figure 4
Closed loop system with unknown parameters.
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Where , , ,, , $x_{1} = v_{c}$ , and $u = E$ .

The transfer function using:

(10)

Yields:

(11)

In equation (11), the following values will be replaced to find the system's response:

(12)

(13)

The poles of equation (13) are:

Closed loop with unknown PID constants: when replacing the parameters in the transfer function and making a change of variables , , , you must close the loop with unknown PID as shown in Figure (4). This yields the transfer function with the unknowns constants of PID:

(14)

In the transfer function (14) there are zeroes that must be canceled so that the system behavior will be equal to the desired transfer function. For this purpose the gain (15) must be cascaded with

(15)

Then

(16)

Is obtained

For matching the characteristic equations, the degree of the desired second order characteristic equation must be increased. This is done by adding a remnant pole so as not to affect the desired behavior significantly.

(17)

The coefficients can be calculated by matching the denominator of (16) with (17):

(18)

Replacing these constants (18) in the closed loop transfer function (16), then the simulation is performed with a step value of $E$ volts. Figure (5) shows the block diagram for PID control simulation.

Figure 5
PID control simulation.
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D. ZAD-FPIC CONTROL TECHNIQUE.

This control technique was proposed by [6], numerically and experimentally tested in [12, 13, 18, 19]. A complete discussion on the design of the ZAD-FPIC controller is presented in [13, 15, 16].

The duty cycle is calculated as follows [13, 19]:

(19)

Where $d_{k}$ is the duty cycle calculated in each iteration and $d^{*}$ is calculated at the beginning of each period as follows:

(20)

The equation (19) incorporates ZAD and FPIC techniques.

Figure (6) shows the block diagram for the ZAD-FPIC control simulation taking into account load estimator presented by [16] p. 4.

Figure 6.
ZAD-FPIC control simulation.
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IV. RESULTS OF THE CONTROLLED BUCK CONVERTER WITH THE PROPOSAL TECHNIQUES.

n Table (1) the parameters of buck converter for the three controllers are shown, figures (7), (8), (9) and (10) shows the performance of the control techniques for the continuos case. The parameters for the PID were calculated in equation (18), but the $K_{i}$ and $K_{d}$ were changed to and respectively in order to compensate for saturation effects. The SMC parameter $c$ was tuned by to get a behavior like that of the PID controller. The ZAD-FPIC technique was implemented using equation (20) and the parameters of Table (1) with $K_{s} = 1$ and $N = 1$ . Figure (8) shows the percentage error obtained by control techniques compared. The SMC also has better stability and all controllers have lower steady-state error.

Load variations in the controller is shown in Figures (9), (10). The load was changed from $R = 40 Ω$ to $R = 10 Ω$ to $t = 4 m s$ . Then, in ZAD-FPIC, a load estimator presented by [16] is necessary, the best controllers to load changes is the SMC and ZAD-FPIC.

TABLE I
SYSTEM PARAMETERS
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Figure 7.
Performance control techniques.
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Figure 8
Error obtained by control techniques.
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Figure (10) shows the duty cycle. The PID and SMC controllers show saturation in the duty cycle most of the time, unlike the ZAD-FPIC controller, which leads to more stable switching frequency in the ZAD-FPIC technique

Figure 9.
Behavior presented with load changes.
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Figure 10.
Duty cycle presented with load changes.
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Figure (11) shows the numerical simulation including experimental limitations. Figures (12), (13), (14) and (15) show the experimental results, in this case the following limitations are present: quantization effects A/D 12 bits and DPWM 9 bits, sampling frequency ( $5 K H z$ ) with 1 delay period, switching frequency ( $5 K H z$ ), ZAD-FPIC parameters are $K_{s} = 4$ and $N = 2$ and also the given in Table (1), PID parameters are , and , SMC parameter is . In discrete time the ZAD-FPIC control has better performance, PID and SMC has very high steady-state error.

Figure 11
Numerical simulation with experimental limitations.
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Figure 12
Experimental performance of controllers.
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Figure 13.
Experimental response for PID controller technique.
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Figure 14
Experimental response for SMC controller technique
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Figure 15.
Experimental response for ZAD-FPIC-estimator controller technique.
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V. CONCLUSIONS

The experimental results showed that the ZAD-FPIC techniques are better for the case where exist limitations such as: sampling, quantization and delay. For the continuous case all the controllers have good performance. When programming the controllers ZAD-FPIC is the most complicated. For the continuous case with load change, the PID controller has more settling time, while the (ZAD-FPIC-without load estimator) does not regulate the output voltage. Through simulations and experiments it was observed that ZAD-FPIC controller has fixed switching frequency for the steady state case. The SMC and PID controllers work very well when devices with high sampling rates.

ACKNOWLEDGMENTS

The authors would like to thank to DIME and DIMA of Universidad Nacional de Colombia—Medellín and Universidad Nacional de Colombia—Manizales for the given support through the projects HERMES-19210, HERMES-36911, and HERMES 34671

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